Dynamic random-access memory (DRAM) systems within three-dimensional (3D) chip architectures comprise one or more DRAM cells which communicate with a memory controller by means of a data bus formed within an interface comprising a silicon interposer (SII) or through silicon vias (TSVs). The wider data bus of the 3D chip architecture is subject to increased variation compared to the data bus of a two-dimensional (2D) chip architecture due to routing mismatch within an SII or TSV balance variation due to differing TSV numbers along different paths.